1. Field of the Invention
This invention related to semiconductor manufacturing. More particularly, this invention relates to a method of planarizing a semiconductor substrate.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is one kind of volatile memory. A DRAM device usually includes an array region comprising plural memory cells and a peripheral region comprising control circuit. Generally, each memory cell has a transistor electrically coupled with a capacitor (1T1C). A digital data is storage in a memory cell by charging or discharging of the capacitor.
In advanced technology node of semiconductor manufacturing, the dimension of a memory cell has been miniaturized by adopting three-dimensional structure. For example, a memory cell having a capacitor (also known as crown-type capacitor) formed vertically stacked on the transistors and having the electrode extending upwardly may occupy a much smaller area of the substrate and may have more flexibility in adjusting the capacitance for different applications. For instance, the overall capacitance of a crown-type capacitor may be increased simply by increasing the height therefore increasing the overlapping area of the electrodes and the capacitance of the capacitor is increased.
However, the height of the crown-type capacitor may cause a large step height of a dielectric layer covering the array region and the peripheral region and adversely increase the difficulty of a following planarization process for planarizing the dielectric layer. Therefore, there is still a need in the field to provide an improved planarization method which is able to effectively remove the large step height and obtain a flat upper surface of the substrate and ensure the uniformity between different substrates.